The present inventive concepts relate to a smart memory architecture, and more particularly to a method and system for providing a smart memory architecture for resistive type memory.
The present inventive concepts relate to memory systems for storing and retrieving information from memory integrated circuits, including static random access memory (SRAM), dynamic random access memory (DRAM), Flash memory, phase-change random access memory (PCRAM), spin-transfer torque random access memory (STT-RAM), magnetic random access memory (MRAM), resistive random access memory (RRAM), and future memory devices. Inventive aspects described herein are particularly well-suited for memories such as STT-RAM, MRAM and RRAM memories, which exhibit probabilistic-type characteristics and relatively high error rates.
Semiconductor memory devices have been widely used in electronic systems to store data. There are two general types of semiconductor memories: non-volatile and volatile memories. A volatile memory device, such as a Static Random Access Memory (SRAM) or a Dynamic Random Access Memory (DRAM), loses its data when the power applied to it is turned off. A non-volatile semiconductor memory device, however, such as a Flash, Erasable Programmable Read Only Memory (EPROM) or a magnetic random access memory (MRAM), retains its charge even after the power applied thereto is turned off. Where loss of data due to power failure or termination is unacceptable, a non-volatile memory is therefore used to store the data.
FIGS. 1A-1D are simplified, schematic cross-sectional illustrations of a magnetic tunnel junction (MTJ) structure 10 used in forming a spin transfer torque (STT) MRAM cell. Referring to FIGS. 1A-1D, an MTJ 10 is shown as including, in part, a reference layer 12, a tunneling layer 14, and a free layer 16. The reference layer 12 and the free layer 16 can be ferromagnetic layers, while the tunneling layer 14 is a nonmagnetic layer. The direction of magnetization of reference layer 12 is fixed during manufacture and therefore does not change during operation of the STT-RAM memory device. However, the direction of magnetization of the free layer 16 can be varied during operation by passing a current of the required strength through the MTJ structure.
In FIG. 1A, the reference layer 12 and the free layer 16 are shown having the same directions of magnetization, i.e., in a parallel magnetic state. In FIG. 1B, the reference layer 12 and the free layer 16 are shown having opposite magnetization directions, i.e., in an anti-parallel state. In FIG. 1C, the reference layer 12 and the free layer 16 are shown having the same magnetization direction (parallel state), with the magnetization direction perpendicular to a plane defined by the interface of free layer 16 and tunneling layer 14. In FIG. 1D, the reference layer 12 and the free layer 14 are shown having opposite magnetization directions (anti-parallel state), where the magnetization directions are perpendicular to a plane defined by the interface of free layer 16 and tunneling layer 14.
To switch from the parallel state, as shown in FIGS. 1A and 1C, to the anti-parallel state, as shown in FIGS. 1B and 1D, the voltage potential of reference layer 12 is increased relative to that of free layer 16. This voltage difference causes spin polarized electrons flowing from free layer 16 to reference layer 12 to transfer their angular momentum and change the magnetization direction of free layer 16 to the anti-parallel state. To switch from the anti-parallel state to the parallel state, the voltage potential of free layer 16 is increased relative to that of reference layer 12. This voltage difference causes spin polarized electrons flowing from reference layer 12 to free layer 16 to transfer their angular momentum and change the magnetization direction of free layer 16 to the parallel state.
To switch from the parallel state to the non-parallel state or vice versa, the voltage applied to MTJ 10 and the corresponding current flowing through MTJ must each be greater than a respective pair of threshold values. The voltage that must exceed a threshold voltage in order for the switching to occur is also referred to as the switching voltage Vc. Likewise, the current that must exceed a threshold current in order for the switching to occur is referred to as the switching current Ic.
As is well known, when free layer 16 and reference layer 12 have the same magnetization direction (i.e., parallel state), MTJ 10 has a relatively low resistance. Conversely, when free layer 16 and reference layer 12 have the opposite magnetization direction (i.e., anti-parallel state), MTJ 10 has a relatively high resistance. This difference in resistance values provides the ability of the MTJ 10 to act as a memory storage device. Due to the physical properties of an MTJ, the critical current required to change an MTJ from a parallel state to an anti-parallel state is often greater than the critical current required to change the MTJ from an anti-parallel state to a parallel state.
FIG. 2A shows a magnetic tunnel junction (MTJ) 10, which forms a variable resistor in an STT-MRAM type memory cell, and an associated select transistor 20, together forming an STT-MRAM cell 30. The MTJ 10 includes a reference or pinned layer 12, a free layer 16, and a tunneling layer 14 disposed between the reference layer 12 and the free layer 16. Transistor 20 is often an NMOS transistor due to its inherently higher current drive, lower threshold voltage, and smaller area relative to a PMOS transistor. The current used to write a “1” in MRAM 30 can be different than the current used to write a “0”. The asymmetry in the direction of current flow during these two write conditions is caused by the asymmetry in the gate-to-source voltage of transistor 20.
In the following description, an MRAM cell is defined as being in a logic “0” state when the free and reference layers of its associated MTJ are in a parallel (P) state, i.e., the MTJ exhibits a low resistance. Conversely, an MRAM cell is defined as being in a logic “1” state when the free and reference layers of its associated MTJ are in an anti-parallel (AP) state, i.e., the MTJ exhibits a high resistance. It will be understood that in other embodiments, the MRAM cell can be defined as being in the logic “0” state when in an AP state, and the logic “1” state when in a P state. Furthermore, in the following, it is assumed that the reference layer of the MTJ 10 faces its associated select transistor, as shown in FIG. 2A.
Therefore, in accordance with the discussion above, a current flowing along the direction of arrow 35 (i.e., the up direction) either (i) causes a switch from the P state to the AP state thus to write a “1”, or (ii) stabilizes the previously established AP state of the associated MTJ. Likewise, a current flowing along the direction of arrow 40 (i.e., the down direction) either (i) causes a switch from the AP state to the P state thus to write a “0”, or (ii) stabilizes the previously established P state of the associated MTJ. It is understood, however, that in other embodiments this orientation may be reversed so that the free layer of the MTJ faces its associated select transistor. In such embodiments (not shown), a current flowing along the direction of arrow 35 either (i) causes a switch from the AP state to the P, or (ii) stabilizes the previously established P state of the associated MTJ. Likewise, in such embodiments, a current flowing along the direction of arrow 40 either (i) causes a switch from the P state to the AP state, or (ii) stabilizes the previously established AP state.
FIG. 2B is a schematic representation of MRAM 30 of FIG. 2A in which MTJ 10 is shown as a storage element whose resistance varies depending on the data stored therein. The MTJ 10 changes its state (i) from P to AP when the current flows along arrow 35, and/or (ii) from AP to P when the current flows along arrow 40.
The voltage required to switch the MTJ 10 from an AP state to a P state, or vice versa, must exceed the critical switching voltage, Vc0. The current corresponding to this voltage is referred to as the critical or switching current Ic0. While the specified critical value Vc0 and related critical switching current Ic0 can be defined in various ways, such values can be selected based on a 50% switching probability of the memory cell within a specified time. In other words, the critical switching current Ic0 can be selected or otherwise determined based on the design of the MTJ 10 and/or based on measurements of the probability of switching at a particular critical value Vc0 and/or switching current Ic0. When the threshold critical switching current Ic0 is satisfied, there can be a 50% chance that the stored memory bit switches values (e.g., from a “0” to a “1” or a “1” to a “0”). An overdrive current is applied to guarantee that switching occurs at an error rate that is acceptable to meet standard reliability expectations. This overdrive current, or switching current, Isw, may be 1.3 times, 1.5 times, 2 times, or more than 2 times the value of Ic0. For example, if the Ic0 for an MTJ device is 7 microamps (uA) at a 20 nanosecond (ns) write pulse width, then the Isw used to reliably switch the states of the MTJ may be 11 uA or greater.
In some cases, the “safe” write current (e.g., where the write error rate is less than about 10e-9) may be 1.5 to 2 times the critical switching current Ic0 for a certain period of time, for example, 10 nanoseconds. To read the bit value back out of the memory cell, a relatively “safe” read current can be applied (e.g., where the read error rate is less than about 10e-9). For example, the “safe” read current may be 0.2 times (i.e., 20%) of the critical switching current Ic0. By way of another example, if the critical switching current Lc0 is 6 microamps (uA), then the write current under a normal operation mode can be at least 12 uA, or thereabout, and the read current under a normal operating mode can be less than 1.2 uA, or thereabout. In this manner, the probability of the memory cell properly switching under a normal write condition is very high, in some cases near 100%. Similarly, the probability of accidentally switching the value of the memory cell under a normal read condition can be very low, in some cases near zero.
Once in the AP state, removing the applied voltage does not affect the state of the MTJ 10. Likewise, to transition from the AP state to the P state under the normal operating mode, a negative voltage of at least Vc0 is applied so that a current level of at least the switching current Ic0 flows through the memory cell in the opposite direction. Once in the P state, removing the applied voltage does not affect the state of the MTJ 10.
In other words, MTJ 10 can be switched from an anti-parallel state (i.e., high resistance state, or logic “1” state) to a parallel state so as to store a “0” (i.e., low resistance state, or logic “0” state). Assuming that MTJ 10 is initially in a logic “1” or AP state, to store a “0”, under the normal operating mode, a current at least as great or greater than the critical current Ic0 is caused to flow through transistor 20 in the direction of arrow 40. To achieve this, the source node (SL or source line) of transistor 20 is coupled to the ground potential via a resistive path (not shown), a positive voltage is applied to the gate node (WL or wordline) of transistor 20, and a positive voltage is applied to the drain node (BL or bitline) of transistor 20.
As mentioned above, MTJ 10 can also be switched from a parallel state to an anti-parallel state so as to store a “1”. Assuming that MTJ 10 is initially in a logic “0” or P state, to store a “1”, under the normal operating mode, a current at least as great or greater than the critical current Ic0 is caused to flow through transistor 20 in the direction of arrow 35. To achieve this, node SL is supplied with a positive voltage via a resistive path (not shown), node WL is supplied with a positive voltage, and node BL is coupled to the ground potential via a resistive path (not shown).
FIG. 3 represents the variation in the MTJ state (or its resistance) during various write cycles. To transition from the P state (low resistance state) to AP state (high resistance state), a positive voltage at least as great or greater than the critical switching voltage Vc0 is applied. Once in the AP state, removing the applied voltage does not affect the state of the MTJ. Likewise, to transition from the AP state to the P state, a negative voltage less than the critical switching voltage Vc0 is applied. Once in the P state, removing the applied voltage does not affect the state of the MTJ. The resistance of the MTJ is Rhigh when it is in the AP state. Likewise, the resistance of the MTJ is Rlow when it is in the P state.
FIG. 4A shows an MTJ 10 being programmed to switch from an anti-parallel state (i.e., high resistance state, or logic “1” state) to a parallel state so as to store a “0” (i.e., low resistance state, or logic “0” state). In this Figure, it is assumed that the MTJ 10 is initially in a logic “1” or AP state. As described above, to store a “0”, a current Isw at least as great or greater than the critical current Ic0 is caused to flow through transistor 20 in the direction of arrow 40. To achieve this, the source node (SL) of transistor 20 is coupled to the ground potential via a resistive path (not shown), a positive voltage VPP is applied to the gate node (WL or wordline) of transistor 20, and a positive voltage VCC is applied to the drain node (BL or bitline) of transistor 20.
FIG. 5 is an exemplary timing diagram of the voltage levels at nodes WL, SL, SN and BL during a write “0” operation, occurring approximately between times 25 ns and 35 ns, and a write “1” operation, occurring approximately between times 45 ns and 55 ns, for a conventional MTJ such as MTJ 10 shown in FIGS. 4A and 4B. The supply voltage VCC is assumed to be about 1.8 volts. The wordline signal WL, as well as the column select signal CS, are shown as having been boosted to a higher VPP programming voltage of 3.0 volts. During the write “0” operation, the voltages at nodes BL, SL and SN are shown as being approximately equal to 1.43V, 0.34V, and 0.88V respectively. During the write “1” operation, the voltages at nodes BL, SL and SN are shown as being approximately equal to 0.23V, 1.43V, and 0.84V respectively. Although not shown, for this exemplary computer simulation, the currents flowing through the MTJ during write “0” and “1” operations are 121 μA and 99.2 μA, respectively.
FIG. 4B shows an MTJ being programmed to switch from a parallel state to an anti-parallel state so as to store a “1”. It is assumed that MTJ 10 is initially in a logic “0” or P state. To store a “1”, a current Isw that is greater than the critical current Ic0 is caused to flow through transistor 20 in the direction of arrow 35. To achieve this, node SL is supplied with the voltage VCC via a resistive path (not shown), node WL is supplied with the voltage VPP, and node BL is coupled to the ground potential via a resistive path (not shown). Accordingly, during a write “1” operation, the gate-to-source voltage of transistor 20 is set to (VWL-VSN), and the drain-to-source voltage of transistor 20 is set to (VSL-VSN). This STT-RAM type memory cell can provide an excellent non-volatile memory solution.
Unfortunately, with STT-RAM or any other type of memory chip, manufacturing or other defects may result in not all memory cells on a memory chip functioning properly. During memory repair, a memory chip may be tested and failed memory elements replaced by redundant memory elements. Typically called laser repair, this memory repair is generally performed after the first wafer sort test. A laser is used to blow the memory fuse banks to disable the defective memory elements and replace them with the redundant elements. Memory repair is not made available to the memory's end-user.
Various memory systems have been proposed to provide memory access, secure data storage, data verification and recovery, data testing, and memory repair. These systems include, for instance, U.S. Pat. No. 6,657,914, entitled “CONFIGURABLE ADDRESSING FOR MULTIPLE CHIPS IN A PACKAGE”; U.S. Pat. No. 6,754,866, entitled “TESTING OF INTEGRATED CIRCUIT DEVICE”; U.S. Pat. No. 7,365,557, entitled “INTEGRATED TESTING MODULE INCLUDING DATA GENERATOR”; U.S. Pat. No. 7,466,160, entitled “SHARED MEMORY BUS ARCHITECTURE FOR SYSTEM WITH PROCESSOR AND MEMORY UNITS”; U.S. Pat. No. 7,466,603, entitled “MEMORY ACCESSING CIRCUIT SYSTEM”; U.S. Pat. No. 7,673,193, entitled “PROCESSOR-MEMORY UNIT FOR USE IN SYSTEM-IN-PACKAGE AND SYSTEM-IN-MODULE DEVICES”; U.S. Pat. No. 7,768,847, entitled “PROGRAMMABLE MEMORY REPAIR SCHEME”; and U.S. Pat. No. 7,779,311 entitled “TESTING AND RECOVERY OF MULTILAYER DEVICE”, the contents of each of which are hereby incorporated by reference in their entirety.
Although these and other systems have addressed similar problems to those addressed by the present inventive principles, they have not been designed for, or applied specifically to, memory with high error rates and probabilistic tendencies such as PCRAM, MRAM, and RRAM devices. In particular, U.S. Pat. No. 7,673,193 describes an apparatus and method for a processor memory unit for use in system-in-package (SiP) and system in module (SiM) integrated circuit devices which includes a processing module, a memory module, and a programmable system module. The programmable system module is configured to function as an interface between the memory module and a testing device to facilitate integration and testing of processor-memory units including functional components having different communication protocols. The interface layer (system module) 120 can include process specific signal processing algorithms for yield enhancement, data compression, test algorithms, power management, etc. This system is particularly useful for multi-chip DRAM plus logic interface products. According to additional features and embodiments incorporating principles of the inventive concept, however, the usefulness of this type of system can be extended to Flash memory, PCRAM, MRAM, RRAM, and future memory devices.